1. Field of the Invention
The invention relates to a method for determining a repair solution for a memory module in a test system. The invention furthermore relates to a test device for determining a repair solution for a memory module which can be connected to the test device.
2. Description of the Related Art
Memory module, in particular memory modules having dynamic memory cells, DRAMs, cannot be fabricated without defects. Thus, after the fabrication of the memory modules, there are always some defective memory cells among the memory cells. In order to be able to repair these defective memory cells, additional memory cells are provided on the memory module. These additional memory cells are called redundant memory cells.
After the memory module has been fabricated, the functioning of the individual memory cells is checked. By writing to and reading from a memory cell, it is possible in this case to identify defective memory cells. The defect in a memory cell is identified by comparing the datum written in with the datum read out, a defect being identified if the datum written in and the datum read out differ from one another. The comparison between the written and read-out data can be effected both in the memory module itself and in the test system.
The comparison data thus generated are called defect data and specify whether a defect is present in a memory cell. It is often the case that only memory areas having a plurality of memory cells can be replaced by redundant memory areas, so that it suffices for a defect datum to specify whether a defect is present in the memory area. The volume of defect data is thereby reduced.
The test sequence is essentially controlled by a test device containing a defect address memory in which the defect data determined are stored. The defect address memory is essentially a mapping of the memory cell array, a memory location of the defect address memory mapping a memory cell or a memory area having a plurality of memory cells of the memory module. A bit which is set in a memory location of the defect address memory then corresponds to one or a plurality of defective memory cells in the memory module. If the bit is not set, then no defect is present.
The defect address memory serves as a basis for the redundant calculation which is used to perform a replacement of the defective memory cells by a disconnection of the defective memory areas and an activation of redundant memory elements. Memory elements may be, by way of example, word line groups comprising one or a plurality of word lines or bit line groups comprising one or a plurality of bit lines. Since the defect address memory stores the defect data for all the memory areas, that is to say also for functional memory areas, a large defect address memory is necessary in the case of parallel testing of a plurality of memory modules with a large storage capacity. Said defect address memory must have fast access times in order not to reduce the test speed and thus to increase the throughput of the test system.